- From: David Schleef <ds_at_schleef.org>
- Date: Thu, 15 Aug 2002 13:07:50 -0700
On Thu, Aug 15, 2002 at 01:26:59PM -0400, Rob Russell wrote: > I can do some basic setup and testing with the board via registers, > but what I really want is to have an external gate cause a hardware > latch (no problem), and then generate an interrupt so I can handle the > value latched to the HW register. The interrupt part I get stuck on. At worst, you can set up link chains that are 1 sample long (or however long is necessary). This is one of the possible ways that could be implemented to handle end-of-scan events in the ni_pcimio. > I am guessing that the MITE chip on the board must be programmed to > relay the interrupt from the NI-TIO to the PCI bus, but NI doesn't seem > to give any information about that in the manual, nor have i been able > to find any related documents anywhere. The tech support there let me > know that register level programming isnt supported. On both the ni_pcimio and ni_pcidio, the DAQ-STC and MITE can cause interrupts completely independently. dave...
Received on 2002-08-15Z19:07:50