- From: Herman Bruyninckx <Herman.Bruyninckx_at_mech.kuleuven.ac.be>
- Date: Fri, 4 Apr 2003 13:41:37 +0200 (CEST)
We are extending the alpha version of the driver for the NI 6601/6602 counter/timer, which was written by J.P. Mellor. And we have some design decisions to make, for which we want your opinion. The 6601 has one NI TIO chip, the 6602 has two. Each of these chips has four counters, but the last one can be configured to be used as a 32 bit DIO. So, how should we define the subdevices? - one counter subdevice for the 6601, two for the 6602, each with an extra subdevice for the DIO? - one counter subdevice, with 4 channels for the 6601 and 8 channels for the 6602; and one (6601) or two (6602) subdevice for the DIO What is the appropriate way to handle the double usage of one 32 bit register? (I.e., as a counter or as a DIO in the case of these 660x boards.) Herman -- K.U.Leuven, Mechanical Engineering, Robotics Research Group <http://people.mech.kuleuven.ac.be/~bruyninc> Tel: +32 16 322480
Received on 2003-04-04Z10:41:37