ni_pcimio low-latency fifo loop-through

• From: Georg Schiesser <georg.schiesser_at_gmx.at>
• Date: Fri, 21 Sep 2007 12:24:13 +0200

Hi,

I have a ni_pcimio pci-6221_37pin and I want to implement a low-level
FIFO loop-through, so that all data from ADC0 is written to DAC0 using
ni_pcimio's interrupt-driven FIFO mode.

In order to keep the latency between AI and AO very low, I must keep the
number of samples in the output FIFO low.

I had a look at the DAQ-STC technical reference manual, but i didn't
find anything suitable. generating interrupts when the fifo is half-full
will result in latencies >= 10ms, and interrupt-on-empty seems to be not
suitable too. I also had a look at waveform staging, but AFAIK this
cannot be used because I cannot modify the FIFO buffer at run-time.

Is there a way to keep track of the number of bytes in the AO fifo?

-- georg

Received on 2007-09-21Z09:24:13